In the manufacture of integrated circuits, copper interconnects are generally formed on a semiconductor substrate using a copper dual damascene process. Such a process begins with a trench being etched into a dielectric layer and filled with a barrier layer, an adhesion layer, and a seed layer. A physical vapor deposition (PVD) process, such as a sputtering process, may be used to deposit a tantalum nitride (TaN) barrier layer and a tantalum (Ta) or ruthenium (Ru) adhesion layer (i.e., a TaN/Ta or TaN/Ru stack) into the trench. The TaN barrier layer prevents copper from diffusing into the underlying dielectric layer. The Ta or Ru adhesion layer is required because the subsequently deposited metals do not readily nucleate on the TaN barrier layer. This may be followed by a PVD sputter process to deposit a copper seed layer into the trench. An electroplating process is then used to fill the trench with copper metal to form the interconnect.
Once the trench is filled, a chemical mechanical polishing (CMP) process is used to remove excess copper metal and excess portions of the barrier and adhesion layers. CMP is well known in the art and generally involves the use of a rotating polishing pad and an abrasive, corrosive slurry on a semiconductor wafer. After a material is deposited on the surface of a semiconductor wafer, the polishing pad and the slurry physically grind flat the microscopic topographic features until the material is planarized, thereby allowing subsequent processes to begin on a flat surface. In many cases the material is further polished by the polishing pad until the material is reduced to a predetermined thickness or until another material is exposed. Chemical reactions that take place between the slurry and the wafer surface further contribute to the planarizing process.
One drawback to the use of CMP for removing the barrier layer and the adhesion layer is that a polishing pad may not polish the entire surface of the wafer in a consistent manner. This causes the surface of the wafer to be uneven with certain areas being overpolished and other areas being underpolished. For instance, when CMP is used for removing the barrier and adhesion layers, the copper metal remaining in the trench is often overpolished or underpolished. A CMP process may also cause significant damage and erosion to the low-k dielectric material below the barrier layer. Furthermore, as line size decreases with interconnect scaling, the probability of bent copper interconnects or other deformations increases when CMP is used.
Conventional etching processes have been attempted to replace CMP of the barrier and adhesion layers. For instance, a wet etch process using concentrated hydrofluoric (HF) acid combined with a strong oxidizer such as HNO3 is often used. Unfortunately, the HF chemistry induces significant loss of dielectric material for silicon-based dielectric materials such as silicon dioxide (SiO2), carbon doped oxide (CDO), porous CDO, plasma tetraethyl orthosilicate (PTEOS), and fluorinated silicon oxide (SiOF). Furthermore, the addition of strong oxidizers is undesirable as the oxidizers tend to increase the loss of copper metal and may cause corrosion defects.
Dry etch processes have also been used. Once such dry etch process uses tetrafluoromethane (CF4) and oxygen (O2) in an argon (Ar) ion plasma. Though the barrier and adhesion layers are removed, this dry etch process tends to cause substantial contamination of the semiconductor wafer and the reactor with non-volatile metal species, such as copper and tantalum species if tantalum is used in the barrier or adhesion layers.
Therefore, an improved method for removing the barrier and adhesion layers is needed that reduces damage to the low-k dielectric material and the copper interconnects.